Damascene method employing multi-layer etch stop layer
US6734116B2 · kind B2 · utility
7Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Feb 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.