Method and system for performing sampling on the fly using minimum cycle delay synchronization
US6734709B1 · kind B1 · utility
2Cited by
1References
26Claims
0Family size
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Key dates
| Filing date | Mar 6, 2003 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable rejection circuitry are used to provide a sufficient pulse width for sampling on the fly the one or more nodes when the one or more bus domain clocks require asynchronous operation. The sample on the fly circuitry is also operable to synchronously sample on the fly the one or more nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.