Logarithmic amplifier
US6734712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | May 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel-summation logarithmic amplifier is described that uses a novel topology of cascaded and parallel amplifiers to achieve extremely high bandwidth. Included in the topology is a unique delay matching scheme for logarithmic amplifiers that is amenable to fabrication in integrated circuit form. The result is flat group delay over broad frequency ranges and different power levels. The resulting log amplifier is suitable for radar applications and for use in high data rate fiber-optic networks. Also described is a unique design process that yields a set of amplifier gains that closely approximate a logarithm. Also described is the novel idea of using a parallel feedback amplifier (PFA) in piecewise-approximate logarithmic amplifiers. This innovation allows for the design of broadband amplifiers with significantly different gains and similar phase characteristics, which is extremely useful when designing high-frequency logarithmic amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.