Balanced distortion reduction circuit
US6734726B2 · kind B2 · utility
5Cited by
37References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Oct 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/32
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for utilizing the distortion generated within a portion of a balanced amplifier to cancel the distortion generated within the whole balanced amplifier. Samples of the signal and distortion from part of the balanced amplifier are combined with a reference signal such that the two signals destructively combine leaving the distortion from the sampled part of the balanced amplifier. The gain and phase of the distortion is then adjusted so that when it is coupled into the input of the other part of the balanced amplifier the distortion generated by both parts of the balanced amplifier are cancelled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.