Direct modulated phase-locked loop

US6734749B2 · kind B2 · utility

Assignee

• Telefonaktiebolaget LM Ericsson (Publ) · SE

Inventors

• Sven Mattisson · Bjärred, SE
• Håkan Eriksson · Täby, SE

Key dates

• Filing date: May 29, 2001
• Grant date: May 11, 2004
• Expiry date: Feb 24, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03C3/095
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.