Single-ended balance-coded interface with embedded-timing
US6734811B1 · kind B1 · utility
13Cited by
4References
41Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 2003 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | May 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.