Address generator for video pixel reordering in reflective LCD
US6734868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Oct 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2352/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.