Method for driving a semiconductor memory
US6735127B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jun 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of driving a semiconductor memory having a semiconductor substrate, spaced apart first and second impurity diffusion regions disposed in partial surface layers of the substrate, a gate electrode, and a gate insulating film between a channel region and the gate electrode. A portion is disposed in a partial area along the longitudinal direction of a path interconnecting the diffusion regions, and a charge trap film and a second insulating film are sequentially stacked, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films. The method has a hole drain step of draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, by applying a hole drain voltage to the gate electrode, higher than a voltage applied to either the first or second impurity diffusion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.