Semiconductor memory device having an SRAM and a DRAM on a single chip
US6735141B2 · kind B2 · utility
2Cited by
11References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.