System and method for pulling electrically isolated memory cells in a memory array to a non-floating state
US6735146B2 · kind B2 · utility
3Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.