Orthogonal transform processor
US6735167B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Dec 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/70935
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An orthogonal transform processor which can be implemented in simple hardware. A data reception unit accepts a pair of source data values at intervals of T. For each given pair of source data values, an adder/subtractor performs addition and subtraction at intervals of T/n, where n is an integer representing the order of the orthogonal transform algorithm being implemented. The resultant data values are stored in some predetermined storage locations defined in a storage unit. A feedback unit reads out such stored data values from the storage unit and feeds them back to the adder/subtractor. When the intended operation stages are finished, a data output unit reads out the data from the storage unit and sends them out as the final result values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.