Time tracking loop for pilot aided direct sequence spread spectrum systems
US6735242B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70701
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A novel design of, and method of operation for, a coherent delay lock loop (DLL) for communication systems that employ a pilot channel or pilot symbols is disclosed. Pilot information is used to produce an estimate of signal phase and thereby remove the need for the magnitude operation within the DLL arms. The disclosed design and method afford better time-tracking performance by avoiding the squaring loss (due to the magnitude operation) encountered in noncoherent DLL designs. Alternative embodiments disclose designs and methods that are robust to signal amplitude variation. A first alternative normalizes a DLL error signal by a computed estimate of the squared magnitude of the pilot signal. A second alternative normalizes the error signal using only the early and late signals and therefore is applicable for noncoherent DLL designs as well as coherent DLL designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.