Digital coherent envelope demodulation of FDMA signals
US6735263B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | May 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/06
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for coherent detection and demodulation of a FDMA signal, that is a superposition of amplitude modulated carriers, is provided. An array of special digital phase-locked loops (PLLs) is implemented in a digital signal processor (DSP) for processing the received signal after it is digitized, and for extracting the envelopes corresponding to each carrier. Each PLL is deliberately made to slowly respond to error signals in order to allow the loop to preserve its phase while the amplitude value of the envelope flips sign. A down-decimation technique is employed in order to reduce the computational load. This is achieved by applying a finite impulse-response filter (FIR) only once per each frame, thereby only a single multiplication of the frame by the vector of filter's taps is employed. A digital generation of sine and cosine sampled waveforms is employed inside a PLL by using a real-time solution of a difference equation. Implementation of the sine and cosine generation inside a PLL provides an automatic control of the sine and cosine phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.