Apparatus and method for address calculation
US6735682B2 · kind B2 · utility
125Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Oct 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3555
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-cycle address generation unit is described to generate linear addresses. The dual-cycle address generation unit includes a first adder to add a product of an index and a scaling factor to an offset and a segment base during a first clock cycle and a second adder to add output of the first adder with a base during a second clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.