Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements
US6735683B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 4, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Oct 4, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.