Method and system for reducing taken branch penalty
US6735689B1 · kind B1 · utility
1Cited by
10References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/322
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.