Apparatus and method for processing interleaving/deinterleaving with address generator and channel encoding system using the same
US6735723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it is provided. The interleaver includes: an interleaving storing unit for storing data sequence; the writing address generating unit for obtaining inter-location offset of a memory on which symbols are to be written in order to perform a writing operation and for generating a writing address to be practically written on, data and a memory control signal; an address offset generating unit for receiving a middle value (MID_OFF) and a start signal from the writing address generating unit, the middle value and the start signal being used for obtaining an offset between an inter-location offset of the memory; a reading address generating unit for generating increasing the address offset generating unit originated signal to as much as a symbol's memory inter-location offset; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing operation needed reading operation, and in a real interleaving operatio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.