Method of deciding error rate and semiconductor integrated circuit device
US6735726B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Sep 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided an error rate select circuit activated in an information sustaining mode, wherein data is read out from a memory circuit comprising dynamic memory cells and inspection bits for detection and correction of an error. If no error is detected, a first detection signal is accumulated in a first direction, that is, the first detection signal is added to a sum. If an error is detected, a second detection signal is accumulated in a second direction, that is, the second direction signal is multiplied by a weight to produce a product before subtracting the product from the sum. If the sum increases in the first direction, exceeding a predetermined value, the refresh period is lengthened by a predetermined incremental time. If the sum decreases in the second direction, becoming smaller than another predetermined value, the refresh period is shortened by a predetermined decremental time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.