Architecture for built-in self-test of parallel optical transceivers
US6735731B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.