Method of fabricating a tiered structure using a multi-layered resist stack and use
US6737202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved and novel method of forming a tiered structure, such as a T-gate structure, including the fabrication of a stabilized resist layer that provides for the prevention of interlayer intermixing with the deposition of subsequent resist layers. The method includes patterning a base resist layer to provide for an opening which will form the stem of the tiered structure and subsequently stabilizing the resist base layer without deforming the stem opening. Next, a resist stack is deposited on an uppermost surface of the stabilized resist layer. Patterning the resist stack provides for an opening on an uppermost layer or portion, and a reentrant profile in a portion of the resist stack adjacent the stabilized resist layer. Metallization and subsequent removal of the resist layers results in a tiered structure, such as a T-gate structure, formed using only low to medium molecular weight, linear polymeric materials such as those used in positive optical resists in optical lithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.