Method for manufacturing nonvolatile semiconductor memory with narrow variation in threshold voltages of memory cells
US6737344B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Nov 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.