High-speed latch with integrated gate
US6737899B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Sep 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356069
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a “sensing” phase, and provides a differential output. The second differential amplifier latches the output during a “latching” phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance. A fourth differential amplifier receives a differential clock signal, and activates the first and second differential amplifiers during the sensing and latching phases, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.