Method and a system to distribute clock signals in digital circuits
US6737902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | May 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.