Duty cycle correction circuit for use with frequency synthesizer
US6737927B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Nov 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.