Method, apparatus, and system to reduce microprocessor power dissipation
US6738675B2 · kind B2 · utility
25Cited by
17References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2000 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Mar 15, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing a microprocessor's power dissipation. In one embodiment a microprocessor includes a clock circuit, a core coupled to said clock circuit, and an on-die logic circuit coupled to said clock circuit to operate independent of a connection for power to said core, the on-die logic circuit includes a snoop request monitor coupled to a bus, and a snooping memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.