Digital system with split transaction memory access
US6738837B1 · kind B1 · utility
13Cited by
4References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Aug 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.