Bus architecture and shared bus arbitration method for a communication device
US6738845B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2000 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Feb 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W74/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.