Network clock emulation in a multiple channel environment
US6738916B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0632
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In one aspect of the invention, a method of emulating a network clock signal in a multiple channel environment includes receiving a plurality of asynchronous signals each associated with one of a plurality of communication channels and storing each of the plurality of asynchronous signals in one of a plurality of buffers, each associated with one of the communication channels, the buffers operable to communicate with a synchronous communication link having a frame rate. The method further comprises identifying one of the plurality of communication channels as a reference channel, determining a current depth of the buffer associated with the reference channel, and altering the frame rate of the synchronous communication link based at least in part on the current depth of the buffer associated with the reference channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.