Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal
US6738922B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2000 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | May 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery unit is used to recover a clock signal from a transmitted data signal. The clock recovery unit includes a phase locked loop (PLL) circuit and a frequency detection circuit. The frequency detection circuit includes a digital phase tracking circuit (DPTC), which uses a rotational phase shifter to shift phase of a variable clock signal from a voltage controlled oscillator in the PLL circuit, in discrete amounts from 0 to 360 degrees, depending on a digital input code provided by a digital accumulator, which receives up or down count signals from a phase comparator. The shifted variable clock signal is provided to a phase/frequency detector, which provides an output to a glitch suppressor to suppress small phase differences prior to providing the output to the PLL circuit. When the frequency difference between the variable clock signal and the reference clock signal is large, the phase/frequency detector drives the frequency in the correct direction. When the frequency difference is small, the DPTC keeps the phase of the shifted variable clock signal aligned to the phase of the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.