Dynamically configurable debug port for concurrent support of debug functions from multiple data processing cores
US6738929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/914
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.