Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US6740964B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2001 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Aug 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package for three-dimensional mounting is provided. The package includes a wiring substrate having a first surface on which a first wiring pattern is formed and a second surface on which a second wiring pattern is formed, the first wiring pattern and second wiring pattern being electrically connected to each other; a semiconductor chip placed on the first surface of the wiring substrate and electrically connected to the first wiring pattern; a sealing resin layer sealing the semiconductor chip and the first wiring pattern; a thickness direction wire passing through the sealing resin layer in a thickness direction and having one end electrically connected to the first wiring pattern and the other end exposed at the surface of the sealing resin layer; and a lower surface connecting electrode formed on the second surface of the wiring substrate and electrically connected to the second wiring pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.