Inverter apparatus
US6741063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Mar 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P21/34
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Induction voltage command Em* is obtained from inverter's primary frequency command &ohgr;1* and torque boost voltage commander produces torque boost voltage command &Dgr;Vz* in accordance with &ohgr;1* while integrator produces reference phase command &thgr;d*. uvw/dq converter detects motor excitation current Id (equivalent of no-load current). Next, deviation of excitation current limitation level command Idmax* and detected Id is inputted to limiter processing unit to produce torque boost voltage compensation value &Dgr;Vc for varying &Dgr;Vz* so that Id is smaller than or equal to Idmax*. Inverted &Dgr;Vz* is set up as a lower limiter value of the limiter processing unit. Next, &Dgr;Vc and &Dgr;Vz* are added to produce final compensated torque boost voltage command &Dgr;Vt* and &Dgr;Vt* and Em* are added to produce q-axis voltage command Vq* of the inverter output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.