Method and apparatus for switching between input clocks in a phase-locked loop
US6741109B1 · kind B1 · utility
38Cited by
4References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Jul 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop receives multiple input clocks, one of which is selected for use by the PLL at any one time. The phase difference(s) between non-selected input clocks and a feedback signal of the PLL, is monitored and stored. When a switch occurs to using a non-selected clock as the input clock of the PLL, the stored phase difference, typically a DC offset value, is injected into the phase-locked loop to compensate for the phase difference between the clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.