Predictive optimizer for DRAM memory
US6741256B2 · kind B2 · utility
13Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2001 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A predictive optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.