Low-noise memory device having a high sampling frequency
US6741281B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2000 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory device including a capacitive element C1, a terminal of which is connected via a switch SW1 to an input intended to receive an input signal Vccd.According to the invention, the switch SW1 comprises a first and a second bipolar transistor T1 and T2 whose main current paths are arranged head to end between the input and capacitive element C1, and is also provided with control means for alternately extracting or injecting current from or into the bases of the first and second transistors T1 and T2. The invention allows memorization of the value of the input signal Vccd at a high sampling frequency and a low noise level as compared with that of known memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.