One-time-programmable bit cell with latch circuit having selectively programmable floating gate transistors
US6741500B2 · kind B2 · utility
17Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Oct 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.