Counter circuit and reset therefor
US6741670B2 · kind B2 · utility
3Cited by
3References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.