Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry
US6742011B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2000 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Feb 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5336
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of odd/even summation circuitry, and a linear array of adders. The apparatus is configured to add a row of partial product bits produced by a multiplier in multiplying a first operand with a second operand. The first array of odd/even summation circuitry produces a first summation of a portion of the partial product bits. The second array of odd/even circuitry produces a second summation of the other partial product bits. The linear array of adders then adds the first summation and the second summation to produce a carry save representation of a product bit (i.e., a bit of the product produced by multiplying the first operand by the second operand).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.