Scalable and flexible method for address space decoding in a multiple node computer system
US6742101B2 · kind B2 · utility
3Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2002 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Oct 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.