Method and system for range matching
US6742105B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | May 25, 2004 |
| Priority date | — |
| Expiry date | Aug 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly fields, or four segments of 4-bit addresses, for comparison with a 16-bit top end boundary that has been divided into quarterly fields and a 16-bit bottom end boundary that has been divided into quarterly fields. Consequently, the range match circuit is able to analyze the entire 16-bit address field in parallel and perform simple combinational logic to determine if the incoming address is within the boundaries described by the top edge and bottom edge of the range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.