Power-on reset circuit
US6744291B2 · kind B2 · utility
23Cited by
25References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.