Patent · US Expired

Global clock tree de-skew

US6744293B1 · kind B1 · utility

10Cited by

5References

9Claims

0Family size

Assignee

APPLIED MICRO CIRCUITS CORPORATION · US

Inventors

Wei Fu · San Diego, US
Joseph Balardeta · Encinitas, US

Key dates

Filing date	Apr 9, 2002
Grant date	Jun 1, 2004
Priority date	—
Expiry date	Oct 1, 2022

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/089
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit and method for de-skewing a global clock tree is disclosed. A circuit uses a digital delay lock loop having an incoming clock input, a local reference clock input, and a clock output providing an output clock signal. The delay lock loop receives an incoming clock signal and aligns it with a local reference clock signal, where the incoming clock signal is a skewed version of the local reference clock signal. The circuit further includes a clock tree for receiving the output clock signal and outputting a global clock signal when the delay lock loop is in lock mode. The output clock signal of the global clock tree represents a phase lock between an incoming clock signal on the incoming clock input and a local reference clock signal input on the local reference clock input.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.