Power-scalable asynchronous architecture for a wave-pipelined analog to digital converter
US6744395B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Nov 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/447
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for converting a signal from analog-to-digital domain. Upon receipt of an ith with triggering signal, where 1≦i≦N, the method includes initiating at least a partial AD operation. Upon completion of the at least partial operation, the method may includes generating and transmitting an ith+1 triggering signal. The ith+1 triggering signal may be adapted to initiate an ith+1 at least partial operation, thereby creating an asynchronous process. The method further includes repeating the above operations until completion of the analog to digital conversion. In some embodiments of the present invention, upon completion of the conversion, i=N and the ith+1 operation is a power-down function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.