Efficient buffer rendering
US6744533B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1999 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Sep 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K15/1856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for efficient buffer rendering. An object mask, typically a character font mask, is aligned with a memory tiling arrangement (1102). A tile map is generated (1104) to indicate active tiles. An active tile is selected (1106) and the portion of the buffer corresponding to the active tile is transferred (1108) from a first memory, typically an off-chip memory, to a second memory, typically an on-chip memory to allow a processor to render the band buffer tile. The portion of the band buffer is rendered (1110) and returned (1112) to the first memory. The next active tile is selected and the process continues until all active tiles have been rendered (1114).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.