Intelligent interleaving scheme for multibank memory
US6745277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network processing device intelligently interleaves packets for read and write access requests in a multibank memory. The system intelligently writes packets into the different memory banks so that the same memory bank is not used for back-to-back packet reads. The last memory bank write is determined for each output queue. This write information is used in combination with look ahead packet read information for a group of packets from the next output queue scheduled to read packets from memory. The scheduler uses all this information to avoid any back-to-back packet read, write, or read/write accesses to the same memory bank. This intelligent packet interleaving scheme preserves memory bus bandwidth normally wasted accessing the same memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.