Memory controller
US6745279B2 · kind B2 · utility
0Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.