Processing packets in cache memory
US6745289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jul 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/822
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for processing data includes a first set of cache memory and a second set of cache memory that are each coupled to a main memory. A compute engine coupled to the first set of cache memory transfers data from a communications medium into the first set of cache memory. The system transfers the data from the first set of cache memory to the second set of cache memory, in response to a request for the data from a compute engine coupled to the second set of cache memory. Data is transferred between the sets of cache memory without accessing main memory, regardless of whether the data has been modified. The data is also transferred directly between sets of cache memory when the data is exclusively owned by a set of cache memory or shared by sets of cache memory. In one implementation, the above-described cache memory arrangement is employed with a compute engine that provides different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.