Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
US6745299B2 · kind B2 · utility
1Cited by
7References
7Claims
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Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.