Method and system for restricting the load of physical address translations of virtual addresses
US6745306B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2000 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Mar 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for protecting data on a computer system uses one or more restricted areas of memory to store proprietary or confidential data. The translation lookaside buffer (TLB) is used to regulate access to the restricted memory. When a TLB miss occurs during the execution of a program, the TLB miss handling logic determines whether the program is attempting to access restricted memory. If so, then the TLB miss handling logic determines whether the program is authorized to have access. If the program is not authorized to have access, then the TLB miss handling logic generates an exception, such as an invalid page fault, and the TLB is not loaded. If the program is authorized to have access to the restricted page, then the TLB is loaded with the appropriate address translation. As long as the translation remains in the TLB, future accesses to the page by an authorized program will require no additional checks and no additional CPU time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.