Guard ring structure for reducing crosstalk and latch-up in integrated circuits
US6747294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Sep 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having very low parasitic current gain includes a guard ring that is used to completely surround a device, such as a power device, that induces parasitic current. The guard ring is formed in a semiconductor body layer such as an epitaxial layer and has a central guard ring of the same type conductivity as that of the body layer and additional flanking rings of the opposite type conductivity. An unbiased configuration of the guard ring based on the above structure is particularly effective in reducing the parasitic gain. The effectiveness of the guard ring, such as the high current performance, is further improved by reducing the resistance between neighboring rings using various methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.